FPGA P4 IP Blocks

Consilia participated in the development of building blocks and IP cores for the design of the FPGA.

For our valuable customer in the networking segment, we have participated in the design and development of the P4 core for FPGA. The system was designed to compile the configurations from the P4 language and build firmware for an FPGA that realized the packet routing or other desired function.

FPGA P4 IP Blocks

Our Task and Challenge

Parameterizable, FPGA vendor independent

P4 is a programming language and stands for Programming Protocol-independent Packet Processor. Unlike C or Python, it is a domain-specific language for network devices (switches, NICs, routers, filters, etc.).

P4 is optimized for network data forwarding. P4 enables a network developer to design complex network routing configurations without extensive knowledge of standard programming languages. Commonly used features include packet filtering, packet routing, header changes, tenant isolation, load balancing, flow control, inband network telemetry, or access control list. It is endorsed by all big players in networking, such as Google or Intel. 

Our task was to analyze the existing system and design a new parameterizable ALU (Arithmetic –Logic Unit) and the parameterizable memory controller for QDR and DDR RAMs. These components were used by the P4 compiler as building blocks to create the desired packet processing path in the FPGA.


High data throughput FPGA components.

We have created parameterizable IP cores that support various networking functionality used by the P4 language compiler. There were several levels of abstraction, and the most advanced constructs of SystemVerilog language were used to keep the cores parameterizable and synthesizable.

Business Value

Easily programmable network device

By creating parameterizable, synthesizable IP cores that can be used by the P4 compiler, the customer got a set of building blocks that could create an optimal packet routing path in FPGA for the fastest packet processing. The level of complexity and parametrization embedded in the HDL code enabled the creation of a simplified P4 compiler.

How It Is Made

SystemVerilog HDL

All IP cores were designed in SystemVerilog and used the latest supported synthesizable constructions of the language that allowed bringing the burden of abstraction and parametrization from SW to HW. The core development was slightly longer compared to the period of pure coding in SW; however, the task was to design cores that enable the fastest packet processing, and this is possible only when the packets are processed by IP cores in hardware (FPGA).


Customer in the networking segment

Implementation period: 2019—2019

In the year 2019, we created several parametrized FPGA components in SystemVerilog used by the P4 compiler that realized various network functionalities.


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